1. Field of the Invention
The present invention generally relates to a processor, a cache memory of the processor and a control method of the processor and, more particularly, to a processor capable of storing trace data, a cache memory of the processor and a control method of the processor.
2. Description of the Related Art
A conventional processor generally includes a core and a cache memory. The core is used to execute programs. The cache memory includes a cache controller and a plurality of cache waysi. Each cache way includes a data RAMi, a tag RAMi and a write-back (WB) address RAMi, which are used to store data frequently used by the core. If the outputted address of the core (including Tag, Set index, Byte Offset) has a value that is identical to the value of the tag RAM of any cache way, a cache hit is established. In this case, the data RAM of the cache way outputs the data of a cache line to the core according to the Set Index. To the contrary, if the outputted address of the core (including Tag, Set index, Byte Offset) has a value that is not identical to the value of the tag RAM of any cache way, a cache miss is established. In this case, a cache replacement policy is used to determine a cache way whose space is made available in order to store the data retrieved from a memory outside of the cache memory (hereinafter referred to as an external memory, such as the main memory), and the data of the data RAM of the cache way is copied to a write buffer. The data of the write buffer is written back to the corresponding address of the external memory when the system is idle.
To minimize the possible abnormalities during the executions of programs, a trace generation unit is often used to debug the core during the phases of designing, verification and mass production of the conventional processor. Some conventional trace generation units generate signals to verify the results of the core executing programs, and temporarily store the verified results in a dedicated memory of the trace generation unit during the verification process. Such conventional trace generation units include TC1766ED and TC1796ED of Infineon Inc, Xtensa of Tensilica Inc, MPC565 of Freescale Inc, V850 of NEC Inc, ETM of ARM Inc, or PDTrace of MIPS Inc.
Although the conventional trace generation units have significant improvements in regard to signal retrieval and data compression in order to reduce the size of the dedicated memory, the dedicated memory still occupies the majority of area of the trace generation unit. In this regard, the conventional processor often includes the trace generation unit only in the phases of designing and verification while omitting the trace generation unit in the phase of mass production in order to reduce the cost. However, this makes it difficult for the processor to debug when an abnormality occurs during the execution of programs.
As described above, it is difficult not only to debug the conventional processor due to the removal of the trace generation unit in the phase of mass production, but also to reduce the cost due to the arrangement of the dedicated memory in the trace generation unit. Thus, it is necessary to improve the conventional processor.